The number of transistors provided in integrated systems (i.e., system-on-chip (SOC)) continues to increase. Automated Test Equipment (ATE) is applied to screen these increasingly large SOCs for manufacturing defects. As SOC size increases more time is required for ATE to achieve test coverage meeting specified device quality goals (DPPM: Defective-Parts-Per-Million). Additional test time adds to the test cost of each device. Due to additional test cost, the cost to produce the device increases, which results in an increase in average-selling-price and/or reduction in profit.